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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-of-8 Decoder/Demultiplexer with Address Latch
High-Performance Silicon-Gate CMOS
The MC74HC137 is identical in pinout to the LS137. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC137 decodes a three-bit Address to one-of-eight active-low outputs. The device has a transparent latch for storage of the Address. Two Chip Selects, one active-low and one active-high, are provided to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and then by using one of the Chip Selects as a data input while holding the other one active. The HC137 is the inverting version of the HC237. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 152 FETs or 38 Equivalent Gates LOGIC DIAGRAM
1 2 3 15 14 13 1-OF-8 DECODER 12 11 10 9 7
16
MC74HC137
N SUFFIX PLASTIC PACKAGE CASE 648-08
1
16 1
D SUFFIX SOIC PACKAGE CASE 751B-05
ORDERING INFORMATION MC74HCXXXN MC74HCXXXD Plastic SOIC
PIN ASSIGNMENT
A0 A1 A2 LATCH ENABLE CS2 CS1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
A0 ADDRESS INPUTS A1 A2
TRANS- PARENT LATCH
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Inputs ACTIVE- LOW OUTPUTS
Y7 GND
LATCH ENABLE
4
FUNCTION TABLE
Outputs X X L L H H L L H H X X X L H L H L H L H X H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H * H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L LE CS1 CS2 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
CHIP- SELECT INPUTS
CS1 CS2
6 5 PIN 16 = VCC PIN 8 = GND
X X L L L L L L L L H
X L H H H H H H H H H
H X L L L L L L L L L
X X L L L L H H H H X
* = Depends upon the Address previously applied while LE was at a low level.
10/95
(c) Motorola, Inc. 1995
1
REV 6
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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MAXIMUM RATINGS*
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MC74HC137
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
VOL
ICC
TA
VIH
VIL
Iin
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Storage Temperature
Power Dissipation in Still Air
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 2)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Plastic DIP SOIC Package
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND Iout = 0 A
Vin = VCC or GND
Vin = VIH or VIL |Iout| |Iout|
Vin = VIH or VIL |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
v
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 1.5 to VCC + 1.5
- 65 to + 150
- 0.5 to + 7.0
2 - 55 Min 2.0 Value
v 4.0 mA v 5.2 mA
v 4.0 mA v 5.2 mA
0 0 0
0
50
25
20
260
750 500
+ 125
1000 500 400
VCC
Max
6.0
VCC V
6.0
6.0
4.5 6.0
2.0 4.5 6.0
4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.1
1.5 3.15 4.2
0.26 0.26
3.98 5.48
0.1 0.1 0.1
1.9 4.4 5.9
0.3 0.9 1.2
8
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 80
v
1.0 1.5 3.15 4.2 0.40 0.40 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
160
v
Unit
A A V V V V
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol tTLH, tTHL tPHL tPLH tPHL tPLH tPHL tPLH Cin Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 2 and 6) Maximum Propagation Delay, Latch Enable to Output Y (Figures 4 and 6) Maximum Propagation Delay, CS1 or CS2 to Output Y (Figures 2, 3 and 6) Maximum Propagation Delay, Input A to Output Y (Figures 1 and 6) Parameter VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.o 2.0 4.5 6.0 -- - 55 to 25_C 250 50 43 175 35 30 195 39 33 150 30 26 240 48 41 170 34 29 10 75 15 13 Guaranteed Limit
High-Speed CMOS Logic Data DL129 -- Rev 6
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
CPD
tr, tf
tsu
tw
th
Power Dissipation Capacitance (Per Package)*
Maximum Input Rise and Fall Times (Figure 2)
Minimum Pulse Width, Latch Enable (Figure 4)
Minimum Hold Time, Latch Enable to Input A (Figure 5)
Minimum Setup Time, Input A to Latch Enable (Figure 5)
Parameter
3 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C Typical @ 25C, VCC = 5.0 V 1000 500 400 100 20 17 80 16 14 50 10 9 Guaranteed Limit 1000 500 400 100 20 17 125 25 21 315 63 54 220 44 37 245 49 42 190 38 33 300 60 51 215 43 37 100 65 13 11 10 95 19 16 1000 500 400 120 24 20 150 30 26 375 75 64 265 53 45 295 59 50 225 45 38 360 72 61 255 51 43 110 22 19 75 15 13 10
v 85_C v 125_C
v 85_C v 125_C
MC74HC137
MOTOROLA Unit Unit pF pF ns ns ns ns ns ns ns ns
MC74HC137
PIN DESCRIPTIONS
ADDRESS INPUTS A0, A1, A2 (Pins 1, 2, 3) Address inputs. These inputs, when the chip is enabled, determine which of the eight outputs is selected. CONTROL INPUTS CS1, CS2 (Pins 6, 5) Chip-Select inputs. For CS1 at a high level and CS2 at a low level, the chip is enabled and the outputs follow the address inputs (Latch Enable = L). For any other combination of CS1 and CS2, the outputs are at a high level. Latch Enable (Pin 4) Latch-Enable input. A high level at this input latches the Address. A low level at this input allows the outputs to follow the data at the Address pins (CS1 = H and CS2 = L). OUTPUTS Y0 - Y7 Active-low outputs. One of these eight outputs is selected when the chip is enabled (CS1 = H and CS2 = L) and the data on the A0, A1, and A2 inputs correspond to that particular output. The selected output is at a low level while all others remain at a high level.
SWITCHING WAVEFORMS
VALID INPUT A tPLH OUTPUT Y 50% 50% tPHL OUTPUT Y VALID VCC GND tf 90% 50% CS2 10% tPHL 90% 50% 10% tTHL tTLH tPLH tr VCC GND
Figure 1.
Figure 2.
tr CS1 tPHL OUTPUT Y tTHL 90% 50% 10% 90% 50% 10%
tf VCC GND tPLH LATCH ENABLE
tw VCC 50% tPLH OUTPUT Y 50% 50% GND tPHL
tTLH
Figure 3.
Figure 4.
TEST POINT VALID VCC INPUT A tsu LATCH ENABLE 50% GND th VCC 50% GND * Includes all probe and jig capacitance DEVICE UNDER TEST OUTPUT CL*
Figure 5.
Figure 6. Test Circuit
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC137
EXPANDED LOGIC DIAGRAM
15
Y0
14 A0 1
Y1
13
Y2
12
Y3
A1
2
11
Y4
10
Y5
9 3 7 LATCH ENABLE 4
Y6
A2
Y7
CS1
6
CS2
5
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC74HC137
OUTLINE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1 8
-A -
16 9
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
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MOTOROLA
CODELINE
6
*MC74HC137/D*
MC74HC137/D High-Speed CMOS Logic Data DL129 -- Rev 6

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